CTS HCSL輸出時鐘振蕩器，靈活性與多元化兼并的CTS公司，憑借著自身的聰明才智，開發(fā)大量高質(zhì)量的晶振產(chǎn)品，同時也擁有快速交付的能力，以及對于產(chǎn)品超強的靈活性，能夠以高于用戶滿意度為最大的標準，致力于為用戶提供高質(zhì)量低損耗的時鐘振蕩器產(chǎn)品為主，高速電流導引邏輯[HCSL]輸出為 在外圍組件互連Express中找到 [PCIe]應用，英特爾和英偉達芯片組 其他人。HCSL是一個差分輸出標準，類似 至LVPECL，提供高阻抗輸出 快速切換時間。其他優(yōu)勢包括與LVDS和相比的平均功耗 LVPECL和低相位抖動性能。

High Speed Current Steering Logic [HCSL] outputs are found in Peripheral Component Interconnect Express [PCIe] applications, Intel and Nvidia chipsets among others. HCSL is a differential output standard, similar to LVPECL, providing a high impedance output with fast switching times. Other advantages include average power consumption when compared to LVDS and LVPECL and low phase jitter performance.

差分輸出有一個15mA電流源，來自開射極或源極，漏極未端接，需要外部50歐姆電阻接地。如果需要，10至30歐姆系列 可以增加電阻來減少過沖或振鈴 波形。參見圖1和圖2。

PCIe是由PCI特別興趣組[PCI SIG]開發(fā)的串行點對點互連標準，最初用于 幫助計算機制造商實施英特爾規(guī)范。然而，由于其低成本和高數(shù)據(jù)吞吐量，PCIe一直是在多個應用標準中采用包括刀片服務器、數(shù)據(jù)存儲 [SATAe & M.2]，嵌入式計算， 3D圖形、網(wǎng)絡[千兆以太網(wǎng)]和通信平臺。在 鑒于其普及性、簡單性和可擴展性；PCIe電氣接口正用于ASICs、FPGAs和SOC。這為設計師提供靈活的有源晶振解決方案在他們的系統(tǒng)中進行高速數(shù)據(jù)傳輸。CTS HCSL輸出時鐘振蕩器

PCIe is a serial point-to-point interconnect standard developed by the PCI Special Interest Group [PCI SIG], originally for the PC market to help computer manufacturers implement the Intel specification. However, due to its low cost and high data throughput, PCIe has been adopted in several application standards including blade servers, data storage [SATAe & M.2], embedded computing, 3D graphics, networking [Gigabit Ethernet], and communication platforms. In view of its popularity, simplicity and scalability; the PCIe electrical interface is being used in ASICs, FPGAs and SoCs. This provides designers with flexible solutions for high speed data transfer in their systems.

基本的PCIe體系結(jié)構(gòu)由兩臺設備之間的數(shù)據(jù)鏈路組成，這兩臺設備可以有1到32條通道。 通道被區(qū)分為x1、x2、x4、x8、x12、x16和x32 PCIe鏈路。每個通道由以下內(nèi)容定義 差分線對，一對用于發(fā)送[Tx],另一對用于接收[Rx]數(shù)據(jù)。A 單個通道將以每周期1位的速率傳輸數(shù)據(jù)，因此增加更多的通道將增加 傳輸速率。參見圖3和圖4。

The basic PCIe architecture consists of a data link between two devices that can have 1 to 32 lanes. The lanes are differentiated as x1, x2, x4, x8, x12, x16 and x32 PCIe links. Each lane is defined by differential pair of wires, one pair for transmitting [Tx] and the other pair for receiving [Rx] data. A single lane will carry data at a rate of 1 bit per cycle, therefore adding more lanes will increase the transfer rate. See figures 3 and 4.CTS HCSL輸出時鐘振蕩器

An external reference clock is required to transmit the data. The standard clock requirements include a frequency of 100MHz, stability ±300ppm maximum and HCSL output. Although the reference clock frequency has remained the same for all PCIe generations, from PCIe1.0 to PCIe4.0, the jitter requirements have improved to support the higher transfer rates in succeeding versions. A history of PCIe clock jitter requirements are outlined in table Table 1, as well as highlighting the new Gen5.0 standard that is developing in 2019. 

參考時鐘的抖動會直接影響器件之間的數(shù)據(jù)傳輸效率。改進 抖動性能有助于消除數(shù)據(jù)傳輸中的延遲 給設計師以靈活性。

PCIe標準是多種應用標準中用于互連外圍設備的核心技術(shù)。隨著PCIe 5.0的開發(fā)，它將使400GE得以大規(guī)模采用 技術(shù)，因為其16通道系統(tǒng)的全雙工帶寬約為128GB/s。這 將成為支持響應時間和高性能的下一代技術(shù)的關(guān)鍵 5G和物聯(lián)網(wǎng)的帶寬需求。