領(lǐng)先同行瑞薩低相噪時鐘振蕩器應(yīng)用，瑞薩提供業(yè)內(nèi)最廣泛和最深入的硅時序產(chǎn)品組合。除了種類繁多的緩沖器和時鐘頻率合成器產(chǎn)品，我們還提供領(lǐng)先的時鐘振蕩器解決方案，以解決幾乎任何應(yīng)用中的時序挑戰(zhàn)。我們的產(chǎn)品組合在模擬和數(shù)字時序領(lǐng)域擁有超過20年的成熟專業(yè)知識，在先進(jìn)的時序技術(shù)中具有最低的相位噪聲和最高的性能。

時序和時鐘IC廣泛應(yīng)用于網(wǎng)絡(luò)、射頻、物聯(lián)網(wǎng)、電信、圖像傳感器、醫(yī)療甚至音頻應(yīng)用。設(shè)計時序IC的外部電路時，我們必須注意電源設(shè)計。就像我們不應(yīng)該給蘭博基尼加滿廉價的汽油一樣，我們也不應(yīng)該用高噪聲電源給低噪聲時序IC供電。

對于上述所有應(yīng)用中使用的定時和時鐘IC，電源通常是電池或5V至AC之間的任何電壓總線。電源電壓通常通過開關(guān)模式電源被逐步降低到適當(dāng)?shù)乃?。這里，一些外部輻射或傳導(dǎo)噪聲可能會耦合到系統(tǒng)中，電源可能會產(chǎn)生自己的內(nèi)部噪聲，導(dǎo)致其輸出電壓攜帶較寬的頻譜，并產(chǎn)生不準(zhǔn)確的時序/時鐘信號。如果不添加強(qiáng)濾波器或低噪聲LDO，我們就不能直接從這種高噪聲電源為任何噪聲敏感的時序或時鐘IC供電，如圖1所示。由于SMD振蕩器尺寸優(yōu)勢、精確的輸出電壓和更好的動態(tài)負(fù)載響應(yīng)，低噪聲LDO始終優(yōu)于大型濾波器.

這種低噪聲LDO通常具有非常高的電源抑制比(PSRR)來阻擋輸入噪聲，并且其自生噪聲也非常低。PSRR是特定頻率下LDO輸入電壓紋波與輸出電壓紋波的比值，通常以對數(shù)形式表示:

PSRR通常隨負(fù)載電流、裕量電壓、輸出電容以及外部噪聲濾波器電容和輸出電壓而變化，具體取決于有源晶振器件。外部電容可以輕松改善高頻PSRR。然而，對于低頻濾波，電容可能變得相當(dāng)大且昂貴，因此選擇在低頻具有非常高PSRR的LDO可能有助于減小電容尺寸。

圖2顯示了不同系統(tǒng)設(shè)置下的PSRR方差。根據(jù)圖2B，PSRR較高，高頻時輸出電容較大，而LDO在低頻時已經(jīng)有很高的PSRR。根據(jù)圖2D，如果在輕負(fù)載下需要更高的PSRR，設(shè)計人員可以在帶隙引腳上增加一個小的低成本電容，不僅可以改善PSRR，還可以改善內(nèi)部噪聲。領(lǐng)先同行瑞薩低相噪時鐘振蕩器應(yīng)用.

圖2 PSRR與其他系統(tǒng)設(shè)置

LDO的另一個重要參數(shù)是內(nèi)部噪聲，它以兩種方式表示。一個是頻譜噪聲密度，這是一條顯示噪聲與頻率關(guān)系的曲線。在射頻等頻譜受管制的應(yīng)用中，噪聲必須控制在“發(fā)射屏蔽”范圍內(nèi)，才能通過認(rèn)證測試。因此，用戶應(yīng)檢查目標(biāo)頻率附近的頻譜噪聲密度曲線。典型的頻譜噪聲圖如圖3所示。

瑞薩發(fā)布兩款超低噪聲LDORAA214020和RAA214023額定電壓為5.5V，2A輸出，現(xiàn)在完全有資格為瑞薩時序和時鐘IC產(chǎn)品組合供電，并且包含在每個評估板的BOM中。下面給出了一些匹配時鐘IC和LDO器件的例子。更多不同電流額定值和性能的低噪聲LDO即將推出。

Renesas offers the broadest and deepest silicon timing portfolio in the industry. In addition to our wide selection of buffers and clock synthesizer products, we deliver leading-edge system timing solutions to resolve timing challenges in virtually any application. With proven expertise spanning more than twenty years in both analog and digital timing, our portfolio features the lowest phase noise and highest performance in advanced timing technology.

The timing and clock ICs are widely used in applications like networking, RF, IoT, telecom, image sensors, medical, and even audio applications. When designing the external circuitry around a timing IC, we must pay attention to the power supply design. Just like we should not fill a Lamborghini with cheap gas, we are not supposed to power our low-noise timing ICs with noisy power supplies.

For timing and clock ICs used in all the mentioned applications, the power source is usually either battery or any voltage bus between 5V to AC. The power source voltage is typically stepped down to an appropriate level through a switch-mode power supply. Here, some external radiated or conducted noise may be coupled into the system and the power supply may generate its own internal noise causing its output voltage to carry a wide frequency spectrum and inaccurate timing/clock signals to be generated. We should not feed any noise-sensitive timing or clock IC directly from such noisy power supply without adding a strong filter or a low-noise LDO, as shown in Figure 1. A low-noise LDO is always preferred over large filters due to size advantage, accurate output voltage and better dynamic load response.

Such low-noise LDO often has very high Power Supply Rejection Ratio (PSRR) to block the incoming noise and it has very low self-generated noise as well. The PSRR is the ratio LDO input voltage ripple vs. output voltage ripple at a specific frequency, and is typically expressed in log form:

The PSRR typically varies with load current, headroom voltage, output capacitor, and, depending on the part, external noise filter capacitor and output voltage. High-frequency PSRR can be easily improved by external capacitors. However, for low-frequency filtering, the capacitor may become quite large and expensive, therefore selecting an LDO with very high PSRR at low frequencies may help reduce the capacitor size.

Figure 2 shows the PSRR variance over various system settings. Per Figure 2B, the PSRR is higher with a larger output capacitor at high frequencies and the LDO already has very high PSRR at low frequencies. Per Figure 2D, if an even higher PSRR at light load is desired, a designer can add a small, low-cost capacitor on the bandgap pin, which improves not only PSRR, but the internal noise as well.

The other important parameter with an LDO is the internal noise, which is indicated in two fashions. One is spectral noise density, a curve that shows noise versus frequency. In applications like RF with regulation on the frequency spectrum, the noise has to be controlled within the “transmit mask” to pass certification testing. Hence, the user should check Spectral Noise Density curves around the frequency of interest. A typical spectral noise chart is shown in Figure 3.

The other is integrated output noise, also commonly called output noise voltage. It is the spectral noise density integrated over a certain frequency range. In applications like ADC or DAC, all the LDO noise from DC to the bandwidth of the system is integrated and computed as a whole to affect the ADC/DAC accuracy. Therefore, total output noise is important for such applications, and a typical chart is shown in Figure 4. Figure 3 and 4 are taken from Renesas low noise LDOs with excellent performance.